Power-Efficient AND-EXOR-INV Based Realization of Achilles' heel Logic Functions

This paper deals with a power-conscious ANDEXOR-Inverter type logic implementation for a complex class of Boolean functions, namely Achilles’ heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications). Keywords—Achilles’ heel functions, AND-EXOR-Inverter logic, CMOS technology, Low power design.